This invention relates to a clock splitter for high speed clocking components, more particularly, an apparatus, method and means for providing matched clock and inverted clock outputs having corresponding rise and fall edge rates, being resistant to load variations, process variations, voltage variations, and temperature variations.
In high speed components, a clock and an inverted clock pair having tightly matched edges is commonly utilized. Loaded inverter chains and logic XNOR/XOR gate pairs are two common, yet unsatisfactory, methods of providing such a clock and an inverted clock pair.
FIG. 3 depicts the prior art loaded inverter chain. Two paths of inverters generate a clock and an inverted clock. The inverted clock path uses an odd number of inversions and the clock uses an even number of inversions. Capacitive loads are added to the inverter outputs and the loads are adjusted so that the inverting path matches the total delay of the non-inverting path. The limitation of the loaded inverter chain is sensitivity to process variations. While the two paths can be adjusted to have equal delay for a given process, voltage, and temperature (PVT.) Corner, the path delays will vary significantly at other PVT. Corners because a load delay is adjusted to equal a propagation delay through an inverter. An inverter delay will vary differently than a wire or load delay over different corners.
FIG. 4a depicts the prior art XNOR logic circuit. An XOR or XNOR circuit is used for both clock and inverted clock. Both circuit outputs connect to a similar circuit. One XNOR input is connected to high (Vcc) and a second XNOR input of a distinct XNOR gate is connected to low/ground (Vss), making the clock inverted in a first path but not inverted in a second path. The inherent limitation in using an XNOR logic circuit is that the internal circuitry of the XNOR provides a different propagation delay path depending on whether the additional input is Vcc or Vss. This is true for most implementations of XNOR and XOR gates, pass gates or CMOS complementary trees.
A typical NOR tree is unbalanced having input devices A and B, shown in FIG. 4, being in series. Complementary series trees as shown in FIG. 4b are used as a remedy effort. Delay differences due to the A input, N-channel device being longer than the B input, N-channel device are compensated in a complementary fashion by the second series stack with the B input, N-channel device on top. The corresponding A and B, P-channel devices are already in parallel. A similar redundancy of a P-channel series stack balances the NOT (A)*NOT(B) side logic The inversion created by devices 1153 and 1154 is not complementary compensated and causes a delay mismatch between the two paths. Attempting to compensate for the inversion has proven to create a more complex and PVT sensitive circuit.